bits-per-wafer

A semiconductor manufacturing metric measuring the total memory capacity produced on a single silicon wafer.

Bits-per-wafer is a key productivity and density metric in the semiconductor memory industry, specifically for DRAM and NAND flash. It measures the total amount of digital storage capacity (bits) that can be successfully fabricated on a single silicon wafer. Increasing bits-per-wafer is the primary driver of cost reduction in memory manufacturing, as it allows a chipmaker to spread fixed clean-room and equipment costs over a larger volume of saleable storage. To improve this metric, manufacturers shrink the physical size of individual memory cells, transition to advanced architectures like 3D NAND stacking, or implement multi-bit cell technologies. Because raw silicon wafers undergo hundreds of complex processing steps, maximizing the density of functioning bits on each wafer directly lowers the cost-per-bit of the finished memory chips. Investors track bits-per-wafer to evaluate a chipmaker's technological leadership, manufacturing execution, and margin potential. A company with a higher bits-per-wafer growth rate than its peers can lower its unit costs faster, allowing it to maintain profitability even during cyclical downturns in memory pricing. Conversely, falling behind in this metric often leads to margin compression and market share loss.

A semiconductor manufacturer processes a 300mm silicon wafer and yields 5,000 functioning DRAM chips. If each chip has a capacity of 8 gigabits (Gb), the total bits produced on that wafer is 5,000 chips multiplied by 8 Gb, which equals 40,000 Gb (or 40 terabits) per wafer.